1. Field of the Disclosure
The present application relates to a liquid crystal display panel.
2. Description of the Related Art
With the development of an information society, the requirements for display devices used to display images have been increased in a variety of manners. As such, flat panel display devices being thinner and lighter weight compared to cathode ray tubes (CRTs) of the related art are being actively researched and manufactured. The flat panel display devices include liquid crystal display (LCD) devices, plasma display devices (PDPs), organic light emitting display (OLED) devices and so on. Among the flat panel display devices, the LCD devices are now widely being used because of features such as small size, light weight, slimness and low power drive.
The LCD device re-aligns liquid crystal molecules in response to data voltages applied through thin film transistors and controls transmittance of each pixel region, in order to display an image. A plurality of gate lines are formed on an LCD panel provided with the thin film transistors. The thin film transistors may be turn-on/off by gate voltages on the respective gate lines.
The gate lines receive the gate voltages from a gate driver. In a recently proposed LCD device of the gate-in-panel (GIP), the gate driver is formed on the LCD panel in order to reduce manufacturing costs and minimize power consumption. Such a gate driver may be driven in a non-overlapping drive mode and an overlapping drive mode.
FIG. 1 is a waveform diagram illustrating a non-overlapping drive mode of the related art. FIG. 2 is a waveform diagram illustrating an overlapping drive mode of the related art.
Referring to FIG. 1, a gate high voltage is sequentially applied to gate lines in synchronization with first and second clock signals CLK1 and CLK2 which maintain alternately with each other a high level in a single horizontal interval. More specifically, the gate high voltage is applied to the first gate line GL1 in synchronization with the first clock signal CLK1. Also, the gate high voltage is applied to the second gate line GL2 in synchronization with the second clock signal CLK2.
Referring to FIG. 2, the gate high voltage is applied to each of the gate lines in two horizontal intervals. The gate high voltage applied to each of the gate lines is synchronized with first and second clock signals CLK1 and CLK2 which each maintain the high level in two horizontal intervals.
The second clock signal CLK2 has a delayed phase of a single horizontal synchronous interval in comparison with the first clock signal CLK1. As such, the first and second clock signals CLK1 and CLK2 overlap with each other by a single horizontal synchronous interval.
In accordance therewith, the width of the gate high voltage applied to the first gate line GL1 partially overlaps with that of the gate high voltage applied to the second gate line GL2. This results from the fact that the gate high voltage on the first gate line GL1 is synchronized with a high level interval of the first clock signal CLK1 and the gate high voltage on the second gate line GL2 is synchronized with the high level interval of the second clock signal CLK2. In other words, the gate high voltage on the first gate line GL1 overlaps with that on the second gate line GL2 by a single horizontal synchronous interval. In this manner, the overlapping drive mode enables the gate high voltages applied to the gate lines to partially overlap with one another.
The overlapping drive mode applies the gate high voltage during a longer interval, compared to the non-overlapping drive mode. As such, an effect of pre-charging the gate lines may be provided. The pre-charging effect may prevent problems due to the delay of the rising time of the gate pulse which is caused by the resistance-capacitance delay on the gate line.
However, it is difficult for the overlapping drive mode to solve problems which are caused by the delay of the falling time of the gate pulse. Due to this, distortion of signals and longitudinal line defects may be generated.